Active matrix liquid crystal display (AMLCD) devices are typically composed of a matrix of liquid crystal pixels arranged horizontally in rows and vertically in columns. Such devices include first and second opposing polarizers, a liquid crystal layer disposed between the polarizers, and substantially transparent electrodes mounted on opposite sides of the liquid crystal (LC) layer so as to selectively energize same in order to create an image for a viewer.
Electronic matrix arrays find considerable applications in AMLCDs. Such AMLCDs generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are liquid crystal display pixels or alternatively the memory cells of an electronically adjustable memory array.
Typically, an isolation device (e.g. TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines.
Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices in LCD arrays. Thin film transistors (TFTs) formed from deposited semiconductors such as amorphous silicon alloys are ideally suited for these applications because they exhibit a high dark resistivity and therefore have low OFF state currents. The leakage currents are low so that high ON-to-OFF current ratios are made possible for effectively isolating non-addressed array pixels from the pixels being addressed.
Structurally, TFTs generally include substantially co-planar source and drain electrodes, a semiconductor material between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted.
Source and drain electrodes in conventional TFT arrays are typically deposited and patterned on a substrate by way of either flat panel steppers or large area scanning projection aligners in order to define a TFT channel length and width between the source and drain. Large area scanning projection aligners using a single large area mask typically cost about half as much as flat panel steppers, and have about twice the manufacturing throughput as the steppers. Conventional scanning projection aligners typically have a resolution of from about 4 to 6 .mu.m while conventional flat panel steppers typically have a resolution of from about 3 to 4 .mu.m. In consideration of costs and manufacturing throughput, it is clear that it would be desirable to utilize scanning projection aligners as opposed to flat panel steppers so as to decrease manufacturing costs and increase production throughput.
TFT channel lengths smaller than those achievable with certain scanning projection aligners are often desirable for reasons to be discussed below. Typically, TFT source-drain channel lengths of about 6 .mu.m can be obtained with the above-referenced scanning projection aligners. However, it is often desirable to achieve channel lengths less than about 6 .mu.m.
The resulting channel length of a TFT is typically larger or longer than the feature size of the aligner used due to overetching of the source and drain. In the case of Mo source-drain metal, for example, the overetch is typically about 1 .mu.m so that a designed channel of 4 .mu.m ends up as a post-processing TFT channel length of about 6 .mu.m. As a result of this, the channel width must be increased accordingly in order to maintain the same ON current because the TFT ON current is proportional to W/L where "W" is the channel width and "L" is the channel length. Accordingly, there exists a need in the art for a TFT (and method of making same) having a channel length smaller than that allowed by the minimum feature size or resolution of the equipment used to manufacture the TFT so that, for example, a 4 .mu.m channel length or less can be achieved using low-cost equipment such as scanning projection aligners (instead of flat panel steppers).
Small TFT channel lengths are desirable for the following reasons. Pixel voltage shift .DELTA.V.sub.p in thin film transistor LCDs after switching off the gate electrode is proportional to the gate-source capacitance (C.sub.gs) of the TFT. .DELTA.V.sub.p can cause flicker, image retention, and gray level non-uniformity in LCD operation. An effective way to reduce C.sub.gs (i.e. parasitic or gate-source capacitance) is by shortening the channel length of the TFT. When a channel length is reduced, the channel width "W" can be reduced proportionally so as to decrease C.sub.gs because C.sub.gs is proportional to the channel width. Such reduction in channel width is permitted while the same I.sub.ON of the TFT is maintained due to the reduced channel length. This reduction in channel width is a major contributor in reducing C.sub.gs.
FIG. 1 is a side elevational cross-sectional view of prior art linear thin film transistor (TFT) 1. A plurality of TFTs 1 are typically arranged on transparent insulating substrate 3 in the form of a matrix array in AMLCD applications. Each TFT 1 includes gate electrode 5 connected to a gate line (not shown) extending in the row direction, drain electrode 7 connected to a drain line (not shown) extending in the column direction, and source electrode 9 connected to transparent pixel electrode 11 independently formed in an area surrounded by the gate and drain lines. Pixel electrode 11 operates in conjunction with an opposing electrode (not shown) on the other side of the liquid crystal layer (not shown) so as to selectively drive the pixel enabling the respective polarizers to transmit or absorb light rays in order to create an image for the viewer. A TFT electrode, to which a data signal is supplied, will be referred to hereinafter as a drain electrode, while the TFT electrode attached to the pixel electrode will be referred to as a source electrode.
More specifically, gate electrode 5 is formed on clear substrate 3. Gate insulating film 13, made of silicon oxide or silicon nitride, for example, is formed on the upper surface of substrate 3 and on the upper surface of gate electrode 5. Semiconductor film 15, made of amorphous silicon (a-Si), for example, is stacked on gate insulating film 13 above gate 5. Drain and source electrodes 7 and 9 respectively are formed on semiconductor film 15. The linear shaped source and drain electrodes are separated from one another by a predetermined distance forming channel length 17. Drain and source electrodes 7 and 9 utilize doped a-Si contact layers 7a and 9a, and drain-source metal layers 7b and 9b respectively, and are electrically connected to semiconductor film 15.
Unfortunately, when TFT 1 is manufactured using, for example, a conventional scanning projection aligner to position the source and drain electrodes on substrate 3, the resulting channel length 17 of TFT 1 cannot be made as small as desired thereby resulting in an undesirably high parasitic capacitance (C.sub.gs). Because drain 7 and source 9 of TFT 1 are deposited and patterned in the same manufacturing step, the resulting channel length 17 of TFT 1 is limited by the feature size or resolution of the lithography used in making the TFT. High parasitic capacitance values for TFTs are undesirable as set forth above because they tend to cause pixel flickering, image retention, and gray scale non-uniformity. As the parasitic capacitance of a TFT is decreased, the pixel voltage shift when the gate is switched off becomes smaller. As the pixel voltage shift decreases, it becomes easier to compensate the top plate voltage to eliminate DC components for all gray levels and across the entire display area.
Flickering results from a small DC component across the pixel electrodes spanning the LC layer. Pure AC voltage across the electrodes is ideal. By reducing C.sub.gs, the DC component across the pixel electrodes can be substantially eliminated or reduced thereby greatly reducing pixel flickering, image retention, and electrochemical degradation of the LC material.
In order to improve such LCD viewing characteristics, it is sometimes necessary to reduce the channel length of the TFT. However, as set forth above, channel length 17 of TFT 1 is limited to a size dictated by the minimum feature size of the lithography used in patterning the source and drain electrodes because the source and drain are deposited and patterned in the same manufacturing step.
In view of the above, it is apparent that there exists a need in the art for an LCD including a TFT array wherein the TFTs in the array have reduced C.sub.gs and are cost effective to manufacture. Such TFTs are achievable in accordance with this invention by way of an improved TFT manufacturing process which results in TFT channel lengths smaller than those obtainable with the minimum feature size of the lithography used, thereby resulting in reduced C.sub.gs values (and increased I.sub.ON /C.sub.gs(ON) values) so that pixel flickering, image retention, and gray scale non-uniformity of the LCD are decreased. It is a purpose of this invention to fulfill the above-described needs in the art by way of an improved TFT and method of manufacturing same, as well as other needs in the art which will become more apparent to the skilled artisan once given the following disclosure.